The Examination of AES S-Box Implementations Using Composite Field Arithmetic on FPGAs
This paper presents an examination of the S-Box transformation in the Advanced Encryption Standard algorithm. The research examined the S-box implementation as a standard look-up table and implemented as combinational logic derived from Composite Field Arithmetic. The study was carried out using an Artix-7 xc7a100tcsg324-1 Xilinx FPGA, programmed using Verilog HDL in the Vivado design suite. The research suggests that using the Composite Field implementation, the s-box required less ram resources at the cost of more power consumption than the standard implementation requires. It also suggests there is further room for research in the effects the implementation has on possible cryptanalysis techniques and heat generation abatement.
Roger A. Ball,
"The Examination of AES S-Box Implementations Using Composite Field Arithmetic on FPGAs"
ETD Collection for Tennessee State University.